CVE-2025-0647

· HIGHAnalyzed

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CVSS v3.1

7.9

EPSS

0.15%

Published

Jan 14, 2026

Modified

Jan 26, 2026

Public PoC / Exploit

All weaponized →

No public PoC or exploit code indexed for this CVE.

Links to public security research (Exploit-DB, Nuclei, Trickest, GitHub) for defensive use only.

Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

CVSS Vector

CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

Weaknesses (CWE)

CWE-226

Affected Products (22)

arm · c1-ultra_firmwarevulnerable

arm · c1-ultra

arm · c1-premium_firmwarevulnerable

arm · c1-premium

arm · cortex-a710_firmwarevulnerable

arm · cortex-a710

arm · cortex-x2_firmwarevulnerable

arm · cortex-x2

arm · cortex-x3_firmwarevulnerable

arm · cortex-x3

arm · cortex-x4_firmwarevulnerable

arm · cortex-x4

arm · cortex-x925_firmwarevulnerable

arm · cortex-x925

arm · neoverse-v2_firmwarevulnerable

arm · neoverse-v2

arm · neoverse-v3_firmwarevulnerable

arm · neoverse-v3

arm · neoverse-v3ae_firmwarevulnerable

arm · neoverse-v3ae

arm · neoverse-n2_firmwarevulnerable

arm · neoverse-n2

References (2)

https://developer.arm.com/documentation/111546

Vendor Advisory

https://graph.volerion.com/view?ID=CVE-2025-0647

Third Party Advisory

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