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Total
3
Critical
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High
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Medium
3
CISA KEV
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When SMT is enabled, certain AMD processors may speculatively execute instructions using a target from the sibling thread after an SMT mode switch potentially resulting in information disclosure.
LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.
Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.